EPM7256AQC208-12
.png "CPLD>EPM7256AQC208-12")
| ： | EPM7256AQC208-12 |
|---|---|
| ： | CPLDs |
| ： | Altera |
| ： | 2.5/3.33.3V 0 |
| ： | - |
| ： | PQFP |
| ： | 9270 |
| ： | YES |
EPM7256AQC208-12
:
EPM7256AQC208-12
Manufacturer:
Altera
Package:
PQFP
Encapsulation:
-
Batch number:
Quantity:
9270
Pricing(UCD):
| TYPE | DESCRIPTION |
| Package / Case | PQFP |
| Surface Mount | YES |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 208 |
| ECCN Code | 3A991 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Additional Feature | YES |
| HTS Code | 8542.39.00.01 |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 220 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 208 |
| Qualification Status | Not Qualified |
| Operating Temperature (Max) | 70°C |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 2.5/3.33.3V |
| Temperature Grade | COMMERCIAL |
| Supply Voltage-Min (Vsup) | 3V |
| Number of I/O | 164 |
| Clock Frequency | 78.1MHz |
| Propagation Delay | 12 ns |
| Programmable Logic Type | EE PLD |
| Number of Gates | 5000 |
| Number of Logic Blocks (LABs) | 16 |
| Output Function | MACROCELL |
| Number of Macro Cells | 256 |
| JTAG BST | YES |
| In-System Programmable | YES |
| Length | 28mm |
| Height Seated (Max) | 4.1mm |
| Width | 28mm |
| RoHS Status | Non-RoHS Compliant |
 | |
| Orignal genuine | Each chip comes from the original factory |
| |
| Main products | Only make original stock |
| |
| Spot inventory | Only make original stock |
| |
| Original stock | Bom Distributio | Affordable Price |
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