EPM5064JC-2
.png "CPLD>EPM5064JC-2")
| ： | EPM5064JC-2 |
|---|---|
| ： | CPLDs |
| ： | Altera |
| ： | 5V 1.27mm P |
| ： | - |
| ： | - |
| ： | 6786 |
| ： | YES |
EPM5064JC-2
:
EPM5064JC-2
Manufacturer:
Altera
Package:
-
Encapsulation:
-
Batch number:
Quantity:
6786
Pricing(UCD):
| TYPE | DESCRIPTION |
| Surface Mount | YES |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Number of Terminations | 44 |
| ECCN Code | EAR99 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Additional Feature | LABS INTERCONNECTED BY PIA; 4 LABS; 64 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK |
| HTS Code | 8542.39.00.01 |
| Terminal Position | QUAD |
| Terminal Form | J BEND |
| Peak Reflow Temperature (Cel) | 220 |
| Supply Voltage | 5V |
| Terminal Pitch | 1.27mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 44 |
| JESD-30 Code | S-CQCC-J44 |
| Qualification Status | Not Qualified |
| Operating Temperature (Max) | 70°C |
| Supply Voltage-Max (Vsup) | 5.25V |
| Power Supplies | 5V |
| Temperature Grade | COMMERCIAL |
| Supply Voltage-Min (Vsup) | 4.75V |
| Number of I/O | 28 |
| Clock Frequency | 50MHz |
| Propagation Delay | 45 ns |
| Organization | 7 DEDICATED INPUTS, 28 I/O |
| Programmable Logic Type | UV PLD |
| Output Function | MACROCELL |
| Number of Macro Cells | 64 |
| JTAG BST | NO |
| Number of Dedicated Inputs | 7 |
| In-System Programmable | NO |
| Length | 16.51mm |
| Height Seated (Max) | 4.57mm |
| Width | 16.51mm |
| RoHS Status | Non-RoHS Compliant |
 | |
| Orignal genuine | Each chip comes from the original factory |
| |
| Main products | Only make original stock |
| |
| Spot inventory | Only make original stock |
| |
| Original stock | Bom Distributio | Affordable Price |
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